Design Verification Engineer (Internship)

Commitment Period: Jan 2026 onwards (Full-time Internship, min. 6 months) Job Description As design verification engineer, you would be part of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation and formal verification. The goal is simple – to achieve zero-defect with the best and smartest approach to the large verification space. Requirements: Disciplined, quality-minded, and highly driven for excellence Excellent team player and good communication skills MSEE/BSEE in Electrical Engineering or Computer Engineering Experience in UVM verification methodology is a plus Knowledge in deep learning algorithms such as CNN / Transformeris a plus Experience in NPU / GPU / DSP verification is a plus Experience in ARM or RISC-V processor systems is a plus Passionate and strong in general programming is a plus Commit at least 6 months full time and preferably 9 months Good understanding of signed and unsigned number system and their operations Strong knowledge of Verilog or system Verilog is required Good background in linear algebra